An IGFET is a semiconductor device in which a gate dielectric layer electrically insulates a gate electrode from a channel zone that extends between a source and a drain in a semiconductor body. The channel zone in an enhancement-mode IGFET is part of a body region, commonly termed the substrate or substrate region, that forms respective pn junctions with the source and drain. In an enhancement-mode IGFET, the channel zone consists of all the semiconductor body material situated between the source and drain. During operation of an enhancement-mode IGFET, charge carriers move from the source to the drain through a channel induced in the channel zone along the upper semiconductor surface. The channel length is the distance between the source and drain along the upper semiconductor surface.
Over the last forty years, the minimum value of IGFET channel length has decreased generally in the manner prescribed by Moore, “Progress in Digital Integrated Electronics,” Tech. Dig., 1975 Int'l Elec. Devs. Meeting, 1–3 Dec. 1975, pages 11–13. Per Moore's “law”, the minimum channel length decreases roughly in proportion to a factor of 1/√2 (approximately 0.7) every three years. IGFETs employed in state-of-the-art integrated circuits (“ICs”) manufactured at volume-production quantities today have minimum channel lengths considerably less than 1 μm, typically 0.25 μm and moving towards 0.18 μm. The minimum channel length for volume-production ICs is expected to be roughly 0.1 μm in eight to ten years.
An IGFET that behaves generally in the way prescribed by the classical model for an IGFET is often characterized as a “long-channel” device. An IGFET is described as a “short-channel” device when the channel length is shortened to such an extent that the IGFET's behavior deviates significantly from the behavior of the classical IGFET model. Both short-channel and long-channel IGFETs are variously employed in ICs. Because drive current generally increases with decreasing channel length, the great majority of IGFETs used in very large scale integration applications are laid out to have as small a channel length as can be reliably produced with the available lithographic technology.
One short-channel effect is roll-off of the threshold voltage. See (a) Yau, “A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFET's”, Solid-State Electronics, October 1974, pages 1059–1069, and (b) Liu et al, “Threshold Voltage Model for Deep-Submicrometer MOSFET's”, IEEE Trans. Elec. Devs., Vol. 40, No. 1, January 1993, pages 86–95. The threshold voltage is the value of gate-to-source voltage at which an IGFET switches between its on and off states for given definitions of the on and off states.
FIG. 1 illustrates a typical example of how threshold voltage VT rolls off for a conventional n-channel enhancement-mode IGFET whose parameters, other than channel length L, are fixed. As FIG. 1 indicates, threshold voltage VT has relatively little variation in the long-channel regime where channel length L is greater than transition value LX approximately equal to 0.4 μm here. When channel length L drops below LX, the IGFET enters the short-channel regime in which threshold voltage VT rolls off sharply to zero.
In designing IGFETs with increasingly reduced channel length, an important trade-off is between drive current and leakage current. The drive current, preferably high, is the current that flows between the source and drain when the IGFET is turned fully on. The leakage current, preferably low, is the current that flows between the source and drain when the IGFET is turned off with the gate electrode electrically shorted to the source. Decreasing the channel length typically leads to an increase in the drive current. However, the leakage current also typically increases when the channel length is reduced.
Due to the foregoing trade-off, a short-channel IGFET is typically designed so that channel length L is of a value close to where threshold voltage VT starts to roll off sharply to zero. An L value of 0.25 μm satisfies this requirement in FIG. 1. The resulting VT value of slightly more than 0.5 V is sufficiently high to enable a 0.25-μm n-channel IGFET to switch reliably between its on and off states. However, threshold voltage VT for an n-channel IGFET having an L value of 0.18 μm, as occurs in the next generation of IGFETs, is approximately 0.2 V. This is too low to be able to reliably turn such a 0.18-μm IGFET off at zero gate-to-source voltage, especially in light of typical manufacturing variations.
The scaling principles developed by Dennard et al, “Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions” IEEE J. Solid-State Circs., Vol. SC-9, No. 5, October 1974, pages 256–268, have been utilized in downsizing IGFETs. In brief, Dennard et al specifies that IGFET dimensions are to be reduced approximately in proportion to a given scaling factor as the average net dopant concentration in the channel zone, i.e., the semiconductor body material situated between the source and drain in an enhancement-mode IGFET, is increased by the scaling factor. The voltages across various parts of the reduced-dimension IGFET are also generally to be reduced in proportion to the scaling factor.
The scaling theory of Dennard et al functions relatively well down to channel length in the vicinity of 1 μm. Unfortunately, certain scaling limitations are encountered when the channel length is reduced significantly below 1 μm. For example, electron tunneling effects preclude reducing the gate dielectric thickness to the value prescribed by the scaling theory.
Also, when the threshold voltage is to be adjusted by simply implanting the channel zone with ions of the same conductivity type as the channel zone, it is typically preferable that the threshold adjust implant be distinguishable from the vertical dopant profile in the bulk of the channel zone. In scaling an IGFET to channel length significantly less than 1 μm according to the theory of Dennard et al, the threshold adjust implant merges inseparably into the vertical dopant profile in the bulk of the channel zone, thereby simply raising the average net dopant concentration in the channel zone by an approximately fixed amount that is largely independent of channel length. Attempting to extend the scaling theory to channel length significantly less than 1 μm does not work well.
Various techniques have been utilized to improve the performance of IGFETs, including those operating in the short-channel regime, as IGFET dimensions are reduced. One performance-improvement technique involves providing an IGFET with a two-part drain for reducing hot carrier injection. FIG. 2 illustrates such a conventional n-channel enhancement-mode IGFET 10 created from a monocrystalline silicon semiconductor body having region 12 of lightly doped p-type body material. IGFET 10 has n-type source 14, n-type drain 16, intervening p-type channel zone 18, gate electrode 20, gate dielectric layer 22, and gate sidewall spacers 24 and 26. Drain 16 consists of heavily doped main portion 16M and more lightly doped extension 16E. Source 14 similarly consists of heavily doped main portion 14M and more lightly doped extension 14E. When IGFET 10 is turned on, electrons travel from source 14 to drain 16 by way of a thin channel induced in channel zone 18 along the upper semiconductor surface.
A pair of depletion regions extend respectively along the drain/body and source/body junctions. Under certain conditions, especially when the channel length is small, the drain depletion region can extend laterally to the source depletion region and merge with it below the upper semiconductor surface. This phenomenon is termed punchthrough. If the drain depletion region punches through to the source depletion region, the operation of the IGFET cannot be controlled with the gate electrode. Accordingly, punchthrough normally needs to be avoided.
One conventional technique for inhibiting punchthrough as channel length is reduced, and also for shifting threshold voltage roll-off to shorter channel length, is to increase the dopant concentration of the channel zone in a pocket portion along the source. See Ogura et al, “A Half Micron MOSFET Using Double Implanted LDD,” IEDM Tech. Dig., Int'l Elec. Devs. Meeting, 11–15 Dec. 1982, pages 718–721. As an artifact of creating the increased-concentration pocket portion along the source, the dopant concentration in the channel zone is commonly increased in a corresponding pocket portion along the drain. Per Codella et al, “Halo Doping Effects in Submicron DI-LDD Device Design,” IEDM Tech. Dig., Int'l Elec. Devs. Meeting, 1–4 Dec. 1985, pages 230–233, the pocket portions are commonly referred to as “halo”.
Increasing the dopant concentration in a halo pocket along the source reduces the thickness of the channel-zone part of the source depletion region, thereby deferring the onset of punchthrough. As the channel length is reduced, the halo pockets along the source and drain get closer together so as to increase the average net dopant concentration in the channel zone. This causes the threshold voltage to increase, thereby partially counteracting threshold voltage roll-off at short channel length.
FIG. 3 depicts a conventional n-channel enhancement-mode halo IGFET 30 as configured in Ogura et al or Codella et al. Except as described below, IGFET 30 contains the same regions as IGFET 10 in FIG. 2. As shown in FIG. 3, channel zone 18 in n-channel IGFET 30 includes a pair of p-type halo pocket portions 31 and 32 doped more heavily than the remainder of channel zone 18. Halo pockets 31 and 32 are situated along the inner boundaries of source 14 and drain 16 so as to inhibit punchthrough. Metal silicide layers 33, 34, and 35 respectively contact main source portion 14M, main drain portion 16M, and gate electrode 20.
Halo pockets 31 and 32 can be created in various ways. For example, p-type halo dopant is typically ion implanted through the upper semiconductor surface into the semiconductor body using gate electrode 20 as an implantation shield. The halo implant can be performed roughly perpendicular to the upper semiconductor surface as indicated in Ogura et al.
The halo implant can also be performed at a substantial angle to a perpendicular to the upper semiconductor surface. In this regard, see (a) Su, “Tilt Angle Effect on Optimizing HALO PMOS Performance,” 1997 Int'l Conf. Simulation Semicon. Procs. and Devs., 8–10 Sep. 1997, pages 33–36, (b) Rodder et al, “A Sub-0.18 μm Gate Length CMOS Technology for High Performance (1.5 V) and Low Power (1.0 V),” IEDM Tech. Dig., Int'l Elec. Devs. Meeting, 8–11 Dec. 1996, pages 563–566, (c) Hori, “A 0.1-μm CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS),” IEDM Tech. Dig., Int'l Elec. Devs. Meeting, 11–14 Dec. 1994, pages 75–78, and (d) Hwang et al, “Degradation of MOSFETs Drive Current Due to Halo Ion Implantation,” IEDM Tech. Dig., Int'l Elec. Devs. Meeting, 8–11 Dec. 1996, pages 567–570.
The threshold voltage of n-channel IGFET 30 is adjusted by introducing p-type dopant, typically boron, into a portion 36 of channel zone 18. The threshold adjust dopant typically has a retrograde dopant concentration profile in that the maximum concentration of the threshold adjust dopant occurs below the upper semiconductor surface. The maximum concentration of the threshold adjust dopant may occur in, or below, a depletion region that extends across channel zone 18 along the upper semiconductor surface during IGFET operation. For example, the information presented in Ogura et al indicates that the maximum concentration of the threshold adjust dopant in Ogura et al occurs in the surface depletion region slightly more than 0.1 μm below the upper semiconductor surface. As a result, the magnitude of the threshold voltage adjustment in Ogura et al is determined primarily by the dosage of the p-type dopant.
Shahidi et al, “High Performance Devices for a 0.15 μm CMOS Technology,” IEEE Elect. Dev. Lett., Vol. 14, No. 10, October 1993, pages 466–468, and Taur et al, “High Performance 0.1 μm CMOS Devices with 1.5 V Power Supply,” IEDM Tech. Dig., Int'l Elec. Devs. Meeting 1993, pages 127–130, describe embodiments of IGFET 30 in which p-type dopant is introduced into channel zone 18 in such a manner that the maximum concentration of the implanted dopant occurs 0.07–0.10 μm below the upper semiconductor surface. Instead of boron, Shahidi et al employs indium, a slow-diffusing species, as the p-type dopant for the implant into channel zone 18. Shahidi also employs indium for the halo pockets. While indium may provide profile steepness and better short-channel behavior, indium is not commonly used in semiconductor manufacturing processes and may cause process implementation difficulties.
Hwang et al, cited above, describes an n-channel IGFET in which a p-type implant is performed relatively deep into the channel zone in order to alleviate punchthrough. The depth of the maximum concentration of the p-type anti-punchthrough implant in this IGFET of Hwang et al appears to occur below the channel surface depletion region. In comparing a halo IGFET to an IGFET having an anti-punchthrough implant but no halo pocket(s), Hwang et al determines that less threshold voltage roll-off occurs in the halo IGFET.
Conventional semiconductor manufacturing processes achieve varying degrees of success in avoiding punchthrough and alleviating threshold voltage roll-off. It is desirable to have an IGFET structure and fabrication technique for overcoming these problems. In so doing, it is desirable to avoid use of semiconductor dopants which are not widely employed in volume-production IC fabrication and which could cause manufacturing difficulties. It is also desirable to have a semiconductor structure in which different IGFETs can readily be provided with different threshold voltages.